The present invention relates to solid-state imaging apparatus, and more particularly relates to the solid-state imaging apparatus for example for use in a digital camera, digital video camera, endoscope, etc.
In recent years, size reduction and power saving of the digital camera/digital video camera or of the endoscope are advanced, making a corresponding size reduction and power saving inevitable of the solid-state imaging apparatus to be used in these. To achieve such a reduction in size and power consumption, solid-state imaging apparatus having an AD conversion circuit formed of digital circuits have been proposed for example in Japanese Patent Application Laid-Open 2006-287879.
FIG. 1 is a block diagram schematically showing construction of a prior-art solid-state imaging apparatus.
In this solid-state imaging apparatus, a pixel section is formed with arranging two-dimensionally or in the illustrated example into 4 rows by 5 columns the array blocks (sub-array) B1, B2, . . . each containing a pixel block 901 where pixel cells having photoelectric conversion device for outputting pixel signal corresponding to incident light amount are two-dimensionally arranged into an array and an AD converter 902 for AD-converting the pixel signal from the pixel block 901.
FIG. 2 is a block diagram showing an example of the circuit construction of the AD converter 902 in FIG. 1. The AD converter 902 includes a delay circuit 911 having delay devices connected into a multiple of stages for giving a delay amount corresponding to input voltage to a running pulse, and an encoder 910 for sampling and encoding the running position of such pulse at every predetermined timing. More particularly, the delay circuit 911 is formed into the manner of a ring so that an output of a predetermined stage of the delay devices is an input to the first stage, and the output of the final stage becomes an input to a counter 912. Further, the encoder 910 more particularly includes the counter circuit 912 for counting the number of times of circulation of the pulse within the delay circuit 911, a latch and encoder circuit 913 for detecting the number of stage at which the running pulse is within the delay circuit 911, and an adder 914 for adding together an output value of the latch and encoder circuit 913 and an output value of the counter circuit 912. An output value from the adder 914 is outputted as an output of the AD converter 902 so as to generate a digital value corresponding to an input voltage according to an input signal. In this case, pixel signals are inputted as input signal.